It is known that, at present, the market for nonvolatile memories, for example of the EEPROM or Flash EEPROM type, is developing and perhaps the most promising applications relate to the data storage field. Until a few years ago, such a market almost exclusively involved the consumer field of digital cameras, with the associated memory cards, or USB portable units, which are expansion mobile memories for personal computers. Therefore, the demand for these products by the consumer market has mainly turned to large capacity flash memories.
This trend seems to be even destined to increase during the next years by virtue of the newer and newer applications of portable electronic devices which require higher and higher memory capacity, for example, for digital cameras or for cell phones of the new generation operating, for example, according to the 3G or UMTS standard. These applications are completely compatible with the natural evolution of Flash memories if one considers that these memories are substantially solid state memory units with further advantages linked to their low power consumption, to their operational silence, and to their reduced space, etc.
The architectures of Flash memories can be substantially referred to two fundamental classes, the first of which relates to the traditional and widely tested NOR architectures, while the second relates to the most innovative and promising NAND architectures. The first ones used to contain the program code and the second ones to contain the data.
For the previously cited applications the most suitable flash architecture for the specifications of low power consumption, high density, high programming and/or erasing speed, is certainly the one of the NAND type. This kind of architecture exhibits obvious advantages with respect to NOR architectures. In particular the Flash memories with the NAND architecture are faster when managing great amounts of data to be recovered in a synchronous way and this makes them most suitable for being used in applications on portable electronic devices.
Since in data storage applications the need of a random access time is less important with respect to the case of “code storage” applications, the most significant feature of NOR architectures loses most of its importance to the advantage of the NAND architecture which allows treating, in a simple and fast way, large amounts of “synchronous” data in reading and programming. However, although having the characteristic of a fast data modify speed, these NAND memories do not allow a fast random access to the same, since they are directed to the reading of whole pages of at least 512 bytes, but not of single bytes.
To meet the growing needs of portable electronic devices it may be necessary to have, in the same memory, also an excellent random access time, such as to perform the code or the boot of the operative system or of the programs without the burdensome assistance of a RAM.
To better understand all the aspects it is to be remembered that the two typologies of memories are both of the floating gate type, i.e. with a portion of conductive material being overlapped onto a control gate and sealed in the oxide, everything arranged above the channel of a MOS device, in general of the N type. The realization and the operation of this type of structure is prior art and allows, by using potentials applied at the different terminals of the cell, to bring or to remove electrons from the floating gate, thus obtaining a modification of the threshold of the equivalent MOS transistor with which logic information can be associated. For example a logic “0” for the presence of electrons and a logic “1” for the absence.
The different architecture of a matrix realized with one or the other of the memory typologies makes the different electrical characteristics more clear. For example, it is important to remember that the reading, i.e. the interpretation of the information contained in the cell, occurs, even if with different modes, by verifying the current the cell is able to absorb.
FIG. 1 shows, by way of example, the structure of a memory of the NOR type characterized in having a drain contact for each cell (in reality, due to space reasons, the contact is shared by two cells); this allows addressing the single cell. The cell reading which occurs as said based upon current, is obtained by biasing the cell and by verifying the current the same is able to absorb.
The arrangement of the cell in the matrix array makes the current to be measured be only for the addressed memory cell. In this way the reading operation uses all the current available and it is thus fast. FIG. 2 schematically shows this approach and also highlights the current flow.
Instead in the case of the NAND architecture, shown for example in FIG. 3, the matrix structure results from the stacked organization of a series of cells, typically sixteen. The reading of the addressed cell involves all the cells of the stack or column. The cell to be read is biased with a higher gate than the others of the same stack, so that these are on while the addressed one, if virgin, will conduct current, if already programmed will not lead and thus operate as a switch to ground discriminating the information logic value.
The presence of such a high number of cells in series, to which the contribution of the selection pass transistors is to be added, implies a reading current being some orders of magnitude smaller than the one in the case of the NOR.
The reading operation thus occurs with a pre-charge and test step, an integration in time which addresses the problem of the measurement precision at the expense of the time necessary to perform it which is of 2-3 orders of magnitude greater than for the NOR case. FIG. 3 schematically illustrates this situation. This FIG. 3 shows in fact a traditional NAND structure wherein, inside the square, hereunder sixteen cells are schematically indicated forming a conventional stack of the NAND structure.
The other fundamental difference between the NOR and the NAND architecture is in the programming mode. In the NOR case the programming is obtained through the physical phenomenon of hot electrons (CHE) while erasing is through the phenomenon known as Fowler-Nordheim tunneling.
In the NAND case both the erasing and the programming occur through tunneling. The two physical phenomena have, as fundamental differences, the execution times and the current used.
In the case of the hot electrons the execution times are on the order of microseconds, while for the tunneling the execution times are on the order of milliseconds. On the contrary, the currents necessary in the case of hot electrons are on the order of tens of microamperes, while those necessary in the case of tunneling are on the order of picoAmperes and they are negligible for electronic devices.
The result of these differences is that the writing, in the NOR case, is faster but the number of cells which are to be programmed in parallel is at least an order of magnitude lower with respect to what can be done in the NAND case. To make an example: 256 cells can be programmed in parallel in a NOR memory, but as many as 4096 cells in the NAND case.
As a consequence, for memories of large size, where one can imagine that the writing operation is made of a byte only but of a lot of words together, the NAND approach is preferred.
This is why the applications are increasingly converging towards a distinction between:
memories for code storage: today densities around 256 Mb, typical reading speed of the NOR, used exactly either as memories from which a download operation of the code to be performed in RAM is carried out or even as execution memories, from here the need of a fast random access; and
memories for data storage, with reading density typical of the NAND, used as data memory banks, for example of photographic cards, where the fast access is not so important since there is no execution of what is downloaded by the Flash but only of an edit on the suitable media; in the case of the photograph it can be the display of a photo on a PC monitor.
Finally, it is to be noted that the organization of the NAND allows a simplification of the erasing operation which is more granular with respect to what is possible for the NOR.
Having both typologies of memories, both the ones for the data storage and those for the code storage, is normally necessary inside an electronic system. Recently further new needs have arisen linked to the game and cellular phone markets, which include having high capacity memories to store any type of data, but also to store a video operative system, programs, results, etc.
To meet these needs the prior art has recently proposed devices defined as the MCP (Multi Chip Package) which incorporate, in a single package, different integrated electronic circuits, such as, for example, several types of memory circuits, for example one Flash memory of the NAND type, one of the NOR type, and a RAM memory.
All these memories are assembled and supplied in a single package so as to provide a single device simultaneously having the advantages of all the commercially available memories, for example, the density and storage capability as regards the NAND portion, or access speed and XIP possibility as regards to the NOR portion, and the random access as regards to the RAM portion.
For example, one of these devices is commercially known with the acronym OneNAND and is manufactured by the company Samsung. Another example of this kind of Multi Chip Package is the “DiskOnChip” of M-System.
Although advantageous under several aspects, and substantially meeting certain desires, these devices are not exempt from drawbacks. In the first place it is to be considered that the various memory circuits to be assembled in a single package are realized with different technologies, which compels addressing compatibility problems in the supplies on a single package and in the management of the input/output signals.
In the second place, the costs of the resulting package cannot significantly depart from the overall cost of the various components, since large scale economies cannot be exploited in realizing devices assembled with components being different from each other.
The problem is that of devising a new type of monolithically integrated electronic memory device, i.e. realized on a single chip, and having such structural and functional characteristics as to offer the same performances of a Multi Chip Package however overcoming the limits and drawbacks of that type of approach.